Taiwan Semiconductor Manufacturing Co (TSMC, 台積電) is in early talks with the German government about potentially establishing a plant in the country, a senior executive said on Saturday.
Various factors, including government subsidies, customer demand and the talent pool, would influence its final decision, TSMC senior vice president of Europe and Asia sales Lora Ho (何麗梅) told reporters on the sidelines of a technology forum in Taipei.
The discussions come as the EU and others seek to increase domestic chip production to mitigate the risk of supply chain disruptions.
Photo: Ann Wang, Reuters
The chipmaker has not discussed incentives with Berlin or decided on a location, Ho said.
TSMC chairman Mark Liu (劉德音) in June told shareholders that the Hsinchu-based company had begun assessments on setting up manufacturing operations in the European country.
The world’s largest contract chipmaker, which mostly produces domestically, has started to diversify over the past year to help meet demand in various major countries seeking to bolster domestic semiconductor production out of national security and self-sufficiency concerns.
It is building a US$12 billion facility in Arizona, and is set to soon start construction of a US$7 billion plant in Japan.
Meanwhile, the EU said it would unveil the “European Chips Act” in the first half of next year as part of its strategy to boost semiconductor production.
One of the goals would be to account for 20 percent of global production by 2030, the bloc said.
Separately, research teams at Intel Corp on Saturday unveiled work that the US company believes would help it keep speeding up and shrinking computing chips over the next 10 years, with several technologies aimed at stacking parts of chips on top of each other.
Intel’s Research Components Group introduced the work in papers at an international conference held in San Francisco.
The company is working to regain a lead in making the smallest, fastest chips that it has lost in the past few years to rivals like TSMC and Samsung Electronics Co.
The newly unveiled research gives a look into how Intel plans to compete beyond 2025.
One of the ways Intel is packing more computing power into chips by stacking up “tiles” or “chiplets” in three dimensions rather than making horizontally designed chips, it said.
Intel showed work that could allow for 10 times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.
However, perhaps the biggest advance showed at the event was a research paper demonstrating a way to stack transistors — tiny switches that form the most basic building blocks of chips by representing the ones and zeros of digital logic — on top of one another.
Intel believes the technology would yield a 30 to 50 percent increase in the number of transistors it can pack into a given area on a chip.
Raising the number of transistors is the main reason chips have consistently gotten faster over the past 50 years.
“By stacking the devices directly on top of each other, we’re clearly saving area,” Intel Components Research Group director Paul Fischer said. “We’re reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing.”
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